About this role

Meet the Team Come join us and be part of the Cisco SiliconOne team and take part in crafting Cisco's groundbreaking Enterprise and Service Provider solutions by crafting some of the most complex chips being developed in the industry with the opportunity to get full exposure to all aspects of the systems and applications we build (Silicon, Hardware, Software, telemetry, security, etc). Our group offers a rare combination of a startup culture with the benefits of working for the top tier networking company in the world! Your Impact Cisco SiliconOne team is looking for an expert and talented ASIC Engineering Technical Leader. You will have an ASIC design verification background with hands-on experience in System Verilog and UVM methodology with in-depth knowledge of C++, scripting as well as ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products.<ul><li>Collaborate closely with the design team and the hardware team to verify the ASIC in simulation, in emulation and during ASIC bring up.</li><li>Defining and Building UVM/System Verilog testbenches from scratch or enhancing existing testbenches with focus on reuse</li><li>Defining new DV methodologies or enhancing the existing methodologies</li><li>In-depth understanding of the architecture, and identification of problems and solutions

</li><li>End-to-end verification of one or more design blocks simultaneously while helping full chip team with integration and support.</li><li>Test plan generation, review, planning and execution, meeting all criteria of ASIC group.</li><li>Help in developing Emulation infrastructure using C/C++, that has to work with UVM based veri

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ASIC Engineering Technical Leader | Design Verification | Verilog, System Verilog, UVM, Testbench | Exp- 12+ Years

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