Senior Engineer

About this role

Job Overview: Experience: 3 – 15 years Responsibilities: Verification engineer with a knowledge of IP verification or SoC integration verification Experience in SoC scenario verification, SoC performance verification, CHI/DDRx/LPDDRx integration verification in SoC RTL. Experience in architecting and implementing SV/UVM testbenches, create and maintain reusable verification components Experience in formal verification strategy for complex IP blocks—defining properties, driving proofs and coverage closure Your key responsibilities will include writing test plans, defining test methodologies, SystemVerilog/Verilog testbench development, developing UVM or C based software tests, and debugging of test failures and issues. Working with project management and leads on planning tasks, schedules, and reporting progress Collaborate with engineers from other teams including architecture, design, implementation, modelling, performance analysis, silicon validation, FPGA and board development Required Skills and Experience : Proven understanding of digital hardware verification language Verilog/Systemverilog HDL Experience in SoC verification using Embedded Low-level programming including C/C++ tests and assembly language(preferably ARM) Experienced in one or more of various verification methodologies – UVM/OVM, Formal(jasper), power aware verification, emulation Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case development, documentation, and support Good Problem Solving and Debugging skills

Knowledge of IP or SoC Verification Flow and strategy. Experience with ARM-based designs and/or ARM System Architectures. Porting peripheral driver software Clock Domain Crossing verification Experienced in GLS, DFT/DFD, Experienced in UPF Power Aware verification Experience in embedded operating systems, device drivers, microprocessor and embedded system hardware architectures

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