About this role

This is a hybrid role with four days per week at Cisco’s Yerevan office.Meet the TeamYou'll be joining our CAD Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This team is a critical part of the group leading the development of high-quality VLSI designs and supports the creation of advanced silicon. Our design center brings together all silicon hardware and software development fields, encouraging collaboration and technical excellence.Your ImpactAs part of our team, you’ll help develop and improve flows for all signoff disciplines and contribute to the evolution of implementation tool flows

You’ll play a key role in enabling the delivery of high-performance, large-scale, and complex devices that push the boundaries of what’s possible in chip design.<ul><li>Develop and refine backend methodologies and flows from RTL to GDS, supporting high-quality VLSI design.</li><li>Contribute to the advancement of all signoff flows, including physical synthesis, place and route, power optimization, timing closure, and physical closure.</li><li>Collaborate with engineering teams to support and enhance implementation tool flows.</li><li>Work with advanced silicon technologies and processes to deliver complex and reliable devices.</li></ul>Minimum Requirements<ul><li>5+ years of experience as a CAD Physical Design Engineer with PnR and STA or as a Design Engineer with strong backend design experience.</li><li>B.Sc. or M.Sc. in Electrical Engineering or Computer Engineering, or a related field.</li><li>Strong understanding of STA flows.</li><li>Familiarity with PnR, physical verification (PV), and formal verification (FV).</li></ul>Preferred Qualifications<ul><li>Experience in Physical Design CA

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Senior Physical Design Engineer - Signoff Methodology

About this role

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