Senior VLSI Design Engineer
Intel Β· ISR - Haifa, Israel
About this role
Job Details: Job Description: About the Team Our team is dedicated to optimizing Intel's process technology to meet evolving Intel designs needs. We drive continuous improvements in silicon designs and methodologies, working at the intersection of process development and design implementation. By partnering closely with Core and SoC design teams, we capture and optimize process requirements to enable competitive, high-performance products
Role Overview As a Senior VLSI Process Design Engineer, you will play a key role in achieving best-in-class power, performance, and area (PPA) for Intel IPs. You will conduct experiments to identify challenges and optimization opportunities in Intel's process technology, evaluate device, cells and blocks, and translate findings into actionable recommendations that influence strategic decision-making and product direction. Key Responsibilities Conduct experiments to identify potential challenges and optimization opportunities in Intel's process technology
Drive continuous improvements to enhance Intel's designs and methodologies across advanced technology nodes. Define methodologies and build tools to optimize PPA of Intel IPs. Analyze PPA results, derive insights, and communicate findings and recommendations to stakeholders, contributing to strategic decision-making and project direction
Collaborate with Core and SoC design teams to capture and optimize process requirements that enable competitive designs and products. Mentor and guide technical teams, foster growth and best practices. Qualifications: BSc or MSc in Electrical Engineering or Computer Engineering
5+ years of hands-on experience in VLSI physical design, with a proven track record of successful projects on advanced technology nodes. Basic scripting languages knowledge such as Python and TCL. Preferred Good familiarity with physical design implementation flows and techniques, including floorplanning, placement, routing, and timing closure
Knowledge at the cell and
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